A typical memory array, such as a flash memory, includes columns of bitlines, which are formed in a substrate, and rows of wordlines, which are situate over and aligned perpendicular to the bitlines. In a flash memory array, memory cells are situated over a channel region, which is formed in the substrate between adjacent bitlines. The memory cells can be, for example, floating gate memory cells, which store charge in a floating gate, or Advanced Micro Devices' (AMD) MirrorBit™ memory cells, which store charge in a nitride layer of an ONO (Oxide-Nitride-Oxide) stack.
In a conventional bitline formation process, bitlines are formed by implanting a dopant into the substrate and activating the dopant in an anneal process, such as a rapid thermal anneal (RTA) process. In addition to activating the dopant, the anneal process is used to repair damage to the crystal structure of the wafer caused by the implant process. However, the anneal process also causes thermal diffusion, whereby dopant diffuses laterally into the channel region. During the anneal process, vertical and lateral dopant diffusion can increase as a result of transient enhanced diffusion (TED). By way of background, TED is an undesirable transient effect wherein the diffusion coefficient of the implanted dopant increases temporarily during post-implantation annealing as a result of crystal structure damage caused by the implant process. Thus, as discussed above, the dopant implantation process and the anneal process used in the conventional bitline formation process cause lateral diffusion of dopant into channel region of the flash memory array.
By causing lateral diffusion of dopant into the channel region, the conventional bitline formation process also undesirably reduce the effective length of the channel region. Since charge is stored above the channel region in a memory cell, reducing the effective length of the channel region also undesirably reduces the effective charge-storing area above the channel region. Reduction of the effective length of the channel region is especially problematic for MirrorBit™ memory cells, since two localized charge regions in each MirrorBit™ memory cell can undesirably affect each other as a result of being closer together. Also, by decreasing the effective channel length, lateral straggle and TED can increase undesirable short channel effects, such as punch through and drain induced barrier lowering (DIBL).
Thus, there is a need in the art for an effective method of forming bitlines in a memory array, such as a flash memory array, that prevents lateral straggle and transient enhanced diffusion caused by a conventional bitline implantation process.